Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach

The challenge of classification confidence estimation in dynamically-adaptive neural networks

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study

A scalable bidimensional randomization scheme for tlc 3d nand flash memories

A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices

A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults

Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits

Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits

A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs

Power efficiency of switch architecture extensions for fault tolerant NoC design

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture

System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic

Testing Resistive Opens and Bridging Faults Through Pulse Propagation

How many test vectors we need to detect a bridging fault?

High quality test vectors for bridging faults in the presence of IC's parameters variations

Delay fault detection problems in circuits featuring a low combinational depth

Pulse propagation for the detection of small delay defects

Diversity analysis in the presence of delay faults affecting duplex systems